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high ip3, 10 mhz to 6 ghz, active mixer ADL5801 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for i ts use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devic es. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. f eatures broadband upconverter/d own c onverter power c onversion g ain of 1.8 db broad band rf, lo, and if ports ssb n oise f igure (nf) of 9.75 db input ip3 : 2 8.5 dbm input p 1db : 13 .3 dbm typical lo d rive : 0 dbm singl e - s upply o peration: 5 v at 13 0 ma adjustabl e bias for l ow p ower o peration exposed p addle , 4 mm 4 mm, 24 - l ead lfcsp p ackage a pplications cellular b ase s tation r eceivers radio link d ownconverters broadband block c onversion instrumentation functional block dia gram gnd vplo enbl vset vpdt gnd rfip nc gnd vplo 7 8 15 16 17 18 21 22 23 ADL5801 19 20 gnd ifon 13 14 deto gnd vprf gnd gnd gnd ifop rfin gnd gnd loip loin 6 5 4 3 2 1 24 9 10 11 12 det v2i 08079-001 figure 1. g eneral description the ADL5801 uses a high linearity, doubly balanc ed, active mixer core with inte grated lo buffer amplifier to provide high dynamic range frequency conversion from 10 mhz to 6 ghz. the mixer benefits from a proprietary linearization architecture that provides enhanced input ip3 performance when subject to high input levels. a bias adjust feature allows the input linearity, ssb noise figure, and dc current to be optimized using a single control pin. an optional input power detector is provided for adaptive bias control. the high input linearity allows the device to be used in demanding cellular applications where in - band blocking signals may otherwise result in degradation in dynamic performance. the adaptive bias feature allows the par t to provide high input ip3 performance when presented with large blocking signals. when blockers are removed, the ADL5801 can automatically bias down to provide low noise figure and low power consumption. the balanced active mixer arrangemen t provides sup erb lo - to - rf and l o- to - if leakage, typically better than ?40 db m . the if outputs are designed to provide a typical voltage conversion gain of 7. 8 db when loaded into a 200 load. the broad frequency range of the open - collector if outputs allows the adl580 1 to be applied as an upconverter for various transmit applications. the ADL5801 is fabricated using a sige high performance ic pro c ess. the device is available in a compact 4 mm 4 mm, 24- lead lfcsp package and operates over a ? 40c to +85c temperature range. an eval uation board is also available.
ADL5801 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 spur performance ....................................................................... 10 circuit description ......................................................................... 11 lo amplifier and splitter .......................................................... 11 rf voltage - to - current (v - to - i) converter ............................. 11 mixer core .................................................................................. 11 mixer output load .................................................................... 11 rf detector ................................................................................. 11 bias circuit .................................................................................. 12 applications information .............................................................. 13 b asic connections ...................................................................... 13 rf and lo ports ......................................................................... 13 if port .......................................................................................... 14 evaluation boa rd ............................................................................ 15 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 2 /10 revision 0: initial versio n
ADL5801 rev. 0 | page 3 of 20 s pecifications v s = 5 v, t a = 25 c, f rf = 900 mhz, f lo = 7 47 mhz, lo power = 0 dbm, z 0 1 parameter = 50 , vset = 3.8 v, unless otherwise noted . table 1 . test conditions min typ max unit rf input interface return loss tunable to >20 db over a limited bandwidth 12 db input impedance 50 rf frequency ra nge 10 6000 mhz output interface output impedance differential impedance, f = 200 mhz 2 3 0 if frequency range can be matched externally to 3000 mhz lf 600 mhz dc bias voltage 2 externally generated 4.75 v s 5.25 v lo interface lo power ? 10 0 + 10 dbm return loss 15 db input impedance 50 lo frequency range 10 6000 mhz power interface supply voltage 4.75 5 5.25 v quiescent current resistor programmable 130 200 ma disable current enbl pin high 50 ma enable time t ime from enbl pin low to enable 182 ns disable time time from enbl pin high to disable 28 ns dynamic performance at f rf = 900 mhz/1900 mhz power conversion gain 3 f rf = 900 mhz 1.8 db f rf = 1900 mhz 1.8 db voltage conversion gain 4 f rf = 9 00 mhz 7.8 db f rf = 1900 mhz 7.8 db ssb noise figure f cent = 900 mhz , vset = 2 . 0 v 9.75 db f cent = 1900 mhz , vset = 2 . 0 v 11.5 db ssb noise figure under blocking 5 f cent = 900 mhz , vset = 2 . 0 v 19.5 db f cent = 1900 mhz , vset = 2 . 0 v 20 d b input third - order intercept 6 f cent = 900 mhz 28.5 dbm f cent = 1 90 0 mhz 26.4 dbm input second - order intercept 7 f cent = 900 mhz 63 dbm f cent = 1 90 0 mhz 49.7 dbm input 1 db compression point f rf = 900 mhz 13.3 dbm f rf = 1900 mhz 12.7 dbm lo -to - if output leakage unfiltered if output ? 27 dbm lo -to - rf input leakage ? 30 dbm rf -to - if output isolation ? 35 dbc if/2 spurious 8 0 dbm input power, f rf = 900 mhz ? 67.5 dbc 0 dbm input power, f rf = 1900 mhz ? 53 dbc 0 dbm input power, f rf = 900 mhz ? 65.5 dbc 0 dbm input power , f rf = 1900 mhz ? 72.6 dbc 1 z 0 is the characteristic impedance assumed for all measurements and the pcb. 2 s upply voltage must be applied from an external circuit through choke inductors . 3 excluding 4:1 if port transformer (tc4 - 1w+ ), rf and lo port transformers (tc1 - 1 - 13m+) , and pcb loss. 4 z source = 50 , differential; z load = 200 differential ; z source is th e impedance of the source instrument; z load is the load impedance at the output. 5 f rf = f cent , f blocker = (f cent ? 5) mhz, f lo = (f cent ? 153) mhz, blocker level = 0 dbm. 6 f rf1 = (f cent ? 1) mhz, f rf2 = (f cent ) mhz, f lo = (f cent C 153 ) mhz, each rf tone at ?10 dbm. 7 f rf1 = (f cent ) mhz, f rf2 = (f cent + 100) mhz, f lo = (f cent C 153 ) mhz, each rf tone at ?10 dbm. 8 for details, see the spur performance section.
ADL5801 rev. 0 | page 4 of 20 absolute maximum rat ings table 2 . parameter rating supply voltage, v pos 5.5 v vset , enbl 5.5 v ifop, ifon 5.5 v rf i n power 20 dbm internal power dissipation 1.2 w ja (exposed paddle soldered dow n) 1 26.5 c/w jc (a t exposed paddle) 8.7 c/w maximum junction temperature 150c operating temperature range ? 40c to +85c storage temperature range ? 65c to +150c 1 as measured on the evaluation board. for details, see the evaluation board section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in t he operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADL5801 rev. 0 | page 5 of 20 pin configuration an d function descripti ons pin 1 indic a t or 1 gnd 2 gnd 3 loi p 4 loin 5 gnd 6 gnd 15 rfin 16 rfi p 17 gnd 18 vprf 14 gnd 13 vpdt 7 vplo 8 gnd 9 enb l 1 1 de t o 12 gnd 10 vset 21 ifon 22 nc 23 gnd 24 vplo 20 ifo p 19 gnd ADL5801 t op view (not to scale) notes 1. there is an exposed p addle th a t must be soldered t o ground. 2. nc = no connec t . 08079-002 figure 2. pin configuration table 3 . pin function descriptions pin no. mnemonic description 1 , 2, 5, 6, 8, 12, 14, 17, 19, 23 gnd device common (dc ground). 3, 4 loip, loin differential lo i nput t erminal. internally matched to 50 . must be ac - coupled. 7, 24 vplo positive supply voltage for lo s ystem . 9 enbl device enable. p ull high to disable the device; p ull low to enable. 10 vset input ip3 bias adjustment. the voltage presented to the vset pin sets the internal bias of the mixe r core and allo ws for adaptive control of the input ip3 and nf characteristics of the mixer core. 11 deto detector output. the deto pin should be loaded with a capacitor to ground. the developed voltage is proportional to the rms input level. when the de to output voltage is connected to the vset input pin , the part auto bias es and increase s input ip3 performance when presented with large signal input levels. 13 vpdt positive supply voltage for detector. 15, 16 rfi n , rfi p differential rf i nput t erminal. internally matched to 50 differential input impedance. must be ac - coupled. 18 vprf positi ve supply voltage for rf input s ystem. 2 0 , 2 1 ifop, ifon differential if output terminal. b ias must be applied through pull - up choke inductors or the center tap of the if transfo r mer. 22 nc not connected. epad the exposed paddle must be soldered to ground.
ADL5801 rev. 0 | page 6 of 20 typical performance characteristics v s = 5 v, t a = 25c, vset = 3.8 v as measured using a typical circuit schematic , unless otherwise noted. insertion loss of input and output bal uns (tc1 - 1 - 13m+, tc4 - 1w+) is extracted from the gain measurement. ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 500 1000 1500 2000 2500 3000 gain (db) rf frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 08079-003 figure 3. power conversion gain vs. rf frequency 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 50 100 150 200 250 gain (db) if frequenc y (mhz) 1900mhz 900mhz 08079-004 figure 4. power conversion gain vs. if frequency 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 2.0 3.0 2.5 3.5 4.0 4.5 5.0 supp l y current (a) gain (db) vset (v) gain = 900m hz gain = 1900m hz i pos = 900m hz i pos = 1900m hz 08079-005 figure 5. power conversion gain and supply current vs. vset 5 10 15 20 25 30 35 0 1 2 3 4 5 6 ?15 ?10 ?5 0 5 10 15 input ip3 (dbm) gain (db) lo leve l (dbm) gain = 900mhz gain = 1900mhz input ip3 = 900mhz input ip3 = 1900mhz 08079-006 figure 6. power conversion gain and input ip3 vs. lo power 0 20 40 60 80 100 10 30 50 70 90 frequenc y (%) 1.700 1.740 1.780 1.820 1.860 1.900 1.940 1.980 2.020 2.060 2.100 power conversion gain (db) 08079-007 mean = 1.87 sd = 0.03 figure 7. power conversion gain distribution 0 0.5 1.0 1.5 2.0 2.5 3.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3 gain (db) supp l y (v) t a = ?40c t a = +85c t a = +25c 08079-008 figure 8. power conversion gain vs. supply voltage
ADL5801 rev. 0 | page 7 of 20 0 5 10 15 20 25 30 35 500 1000 1500 2000 2500 3000 input ip3 (dbm) rf frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 08079-009 figure 9. input ip3 vs. rf frequency 10 15 20 25 30 35 40 0 50 100 150 200 250 input ip3 (dbm) if frequenc y (mhz) 900mhz 1900mhz 08079-010 figure 10 . input ip3 vs. if frequency 8 10 12 14 16 18 20 0 5 10 15 20 25 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 noise figure (db) input ip3 (dbm) vset (v) input ip3 = 900mhz input ip3 = 1900mhz nf = 900mhz nf = 1900mhz 08079-011 figure 11 . input ip 3 and noise figure vs. vset 0 10 20 30 40 50 60 70 500 1000 1500 2000 2500 3000 input ip2 (dbm) rf frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 08079-012 fi gure 12 . input ip2 vs. rf frequency 0 10 20 30 40 50 60 70 80 0 50 100 150 200 250 input ip2 (dbm) if frequenc y (mhz) 900mhz 1900mhz 08079-013 figure 13 . input ip2 vs. if frequency 0 10 20 30 40 50 60 70 80 2.0 2.5 3.5 3.0 4.0 4.5 5.0 input ip2 (dbm) vset (v) 1900mhz 900mhz 08079-014 figure 14 . input ip2 vs. vset
ADL5801 rev. 0 | page 8 of 20 0 2 4 6 8 10 12 14 16 18 20 500 1000 1500 2000 2500 3000 input p1db (dbm) rf frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 08079-015 figure 15 . input p1db vs. rf frequency 0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 input p1db (dbm) if frequenc y (mhz) 900mhz 1900mhz 08079-016 figure 16 . input p1db vs. if frequency 0 2 4 6 8 10 12 14 16 18 500 1000 1500 2000 2500 3000 ssb noise figure (db) rf frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 08079-017 figure 17 . ssb noise figure vs. rf frequency (vset = 2.0 v) 0 5 10 15 20 25 0 100 200 300 400 500 600 700 ssb noise figure (db) if frequenc y (mhz) 1900mhz 900mhz 08079-018 figure 18 . ssb noise figure vs. if frequency (vset = 2.0 v) 0 5 10 15 20 25 30 ?30 ?25 ?20 ?15 ?10 ?5 0 5 ssb noise figure (db) blocker leve l (dbm) 08079-019 rf = 951mhz, if = 153 mhz blocker = 946mhz rf = 1846mhz, if = 153 mhz blocker = 1841mhz figure 19 . ssb noise figure vs. b locker level (vset = 2.0 v) 0 2 4 6 8 10 12 14 16 18 20 ?15 ?10 ?5 0 5 10 15 ssb noise figure (db) lo leve l (dbm) 900mhz 1900mhz 08079-020 figure 20 . ssb noise figure vs. l o power (vset = 2.0 v)
ADL5801 rev. 0 | page 9 of 20 35 30 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 rf return loss (db) rf frequenc y (mhz) 08079-021 figure 21 . rf return loss vs. rf frequency 35 30 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 lo return loss (db) lo frequenc y (mhz) 08079-022 figure 22 . lo return loss vs. lo frequency 08079-023 100 1000 10 3000 100 200 300 400 0 500 ?4 ?2 0 2 ?6 4 if frequenc y (mhz) resis t ance ( ?) ca p aci t ance (pf) figure 23 . if differential output impedance (r parallel c equivalent) ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 500 1000 1500 2000 2500 3000 lo- t o-if leakage (dbm) lo frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 08079-024 figure 24 . lo - to - if leakage vs. lo frequency ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 500 1000 1500 2000 2500 3000 lo- t o-rf leakage (dbm) lo frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 08079-025 figure 25 . lo - to - rf leakage vs. lo frequency ?60 ?50 ?40 ?30 ?20 ?10 0 500 1000 1500 2000 2500 3000 rf- t o-if output isol a tion (dbc) rf frequenc y (mhz) t a = +85c t a = +25c t a = ?40c 08079-026 figure 26 . rf - to- if leakage vs. rf frequency
ADL5801 rev. 0 | page 10 of 20 spur performance all spur tables are (n f rf ) ? (m f lo ) and were measured using the standard evaluation board (see the evaluation board section) . mixer spurious products are measured in decibels relative to the carrier (dbc) from the if output power level. data was measured for frequencie s less than 6 ghz only . the t ypical noise floor of the measurement system is ?100 dbm . 900 mhz performance v s = 5 v, vset = 3.8 v, t a = 25c, rf power = 0 dbm, lo power = 0 dbm, f rf = 90 0 mhz, f lo = 7 0 3 mhz, z 0 = 50 ?. m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 ? 33.1 ? 23.3 ? 45.8 ? 23.6 ? 45.9 ? 30.7 ? 55.4 ? 41.5 1 ? 4 8.8 0.0 ? 51.5 ? 19.0 ? 65.1 ? 29.6 ? 78.0 ? 50.3 ? 74.4 ? 57.7 2 ? 35.9 ? 74.9 ? 67.5 ? 66.1 ? 73.5 ? 80.5 ? 65.0 ? 89.8 ? 71.3 ? 88.5 ? 86.8 ? 98.8 3 ? 68.8 ? 64.8 ? 94.3 ? 65.9 ? 86.3 ? 70.2 ? 76.3 ? 70.6 ? 74.5 ? 81.4 ? 100 ? 99.6 ? 100 4 ? 47.5 ? 80.7 ? 78.0 ? 78.4 ? 95.1 ? 73.5 ? 89.4 ? 87.3 ? 100 ? 92.7 ? 99.5 ? 99.4 ? 100 ? 100 5 ? 95.6 ? 74.7 ? 89.8 ? 70.7 ? 84.8 ? 90.7 ? 86.7 ? 86.4 ? 83.1 ? 73.7 ? 78.7 ? 80.7 ? 91.1 ? 100 ? 100 6 ? 85.7 ? 96.4 ? 83.1 ? 98.5 ? 83.3 ? 96.7 ? 100 ? 89.4 ? 99.6 ? 96.1 ? 96.1 ? 95.4 ? 95.5 ? 100 ? 100 n 7 ? 100 ? 100 ? 95.9 ? 100 ? 97.2 ? 83.1 ? 84.1 ? 100 ? 100 ? 99.7 ? 87.9 ? 88.8 ? 85.7 ? 100 8 ? 100 ? 100 ? 99.0 ? 99.8 ? 86.0 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 9 ? 100 ? 100 ? 100 ? 9 0.9 ? 88.4 ? 83.5 ? 87.6 ? 100 ? 100 ? 100 ? 100 ? 1 00 10 ? 100 ? 100 ? 100 ? 97.9 ? 95.5 ? 99.0 ? 100 ? 100 ? 100 ? 100 11 ? 100 ? 100 ? 92.6 ? 87.4 ? 88.2 ? 92.3 ? 99.3 ? 100 ? 100 12 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 13 ? 100 ? 100 ? 95.1 ? 96.5 ? 90.4 ? 100 14 ? 100 ? 100 ? 100 ? 100 ? 100 15 ? 100 ? 100 ? 100 ? 100 1900 mhz performance v s = 5 v, vset = 3.8 v, t a = 25c, rf power = 0 dbm, lo power = 0 dbm, f rf = 190 0 mhz, f lo = 1703 mhz, z 0 = 5 0 ?. m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 ? 31.4 ? 17.1 ? 51.4 1 ? 40.4 0.0 ? 53.6 ? 38.5 ? 71.0 2 ? 38.4 ? 66.0 ? 52.9 ? 68.1 ? 64.2 ? 86.8 3 ? 100 ? 66.2 ? 73.2 ? 72.6 ? 79.9 ? 65.2 ? 92.8 4 ? 100 ? 89.4 ? 86.4 ? 94.6 ? 87.4 ? 81.5 ? 100 5 ? 83.7 ? 66.2 ? 79.3 ? 89.0 ? 75.2 ? 100 ? 100 6 ? 100 ? 86.4 ? 100 ? 99.0 ? 87.7 ? 100 ? 100 n 7 ? 100 ? 92.4 ? 92.7 ? 100 ? 98.4 ? 100 ? 100 8 ? 100 ? 100 ? 97.5 ? 100 ? 95.4 ? 100 ? 100 9 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 10 ? 100 ? 97.2 ? 95.6 ? 100 ? 100 ? 100 ? 100 11 ? 100 ? 100 ? 100 ? 100 ? 100 ? 100 12 ? 100 ? 100 ? 100 ? 100 ? 100 13 ? 100 ? 100 ? 100 ? 100 14 ? 100 ? 100 15 ? 100
ADL5801 rev. 0 | page 11 of 20 circuit description the ADL5801 includes a double - balanced active mixer wit h a 50 input impedance and 250 output impedance. in addition , the ADL5801 integrates a local oscillator (lo) amplifier and a n rf power detector that can be used to optimize the mixer dynamic range. the rf and lo are differential, providing max - imum us able bandwidth at the input and output ports. the lo also operates with a 50 input impedance and can, optionally, be operated differentially or single ended. the input, output, and lo ports can be operated over an exceptionally wide frequency range. the ADL5801 can be configured as a downconvert mixer or as an upconvert mixer. the ADL5801 can be divided into the following sections : t he lo amplifier and splitter , t he rf voltage - to - current (v - to - i ) converter, the mixer core , the output loads , the rf detecto r, and the bias circuit. a simplified block diagram of the device is shown in figure 27. the lo block generates a pair of differential lo signals to drive two mixer cores . the rf input power is conv erted into rf currents by th e v - to - i converte r that then feed into the two - mixer core . the internal differential load of the mixer provides a wideband 250 output impedance from the mixer . reference currents to each section are generated by the bias circuit, which can be enabled or disabled using the enbl pin. a detailed description of each section of the ADL5801 follows. gnd vplo enbl vset vpdt gnd rfip nc gnd vplo 7 8 15 16 17 18 21 22 23 ADL5801 19 20 gnd ifon 13 14 deto gnd vprf gnd gnd gnd ifop rfin gnd gnd loip loin 6 5 4 3 2 1 24 9 10 11 12 det v2i 08079-127 figure 27 . block diagram lo amplifier and splitt er the lo input is conditioned by a series of amplifiers to provide a well controlled an d limited lo swing to the mixer core, result - ing in excellent input i p3. the lo input is amplified using a broadband low noise amplifier ( lna ) and is then followed by lo limiting amplifier s. the lna input impedance is nominally 50 . the lo circuit exhibits low additive noise, result ing in an excellent mixer noise figure and output noise under rf blocking . for optimal performance, the lo inputs should be driven differentially but at lower freq u encies; single - ended drive is acceptable . rf voltage - to - current (v - to - i ) converter the differential rf input signal is applied to a v - to - i converter that converts the differential input voltage to output currents. the v - to - i converter provides a 50 ? input impedance . the v - to - i section bias current can be adjusted up or down using the vset pin. adju sting the current up improves ip3 and p1db input but degrades the ssb noise figure . adjusting the current down improves the ssb noise figure but degrades ip3 and p1db input . conversion gain remains nearly constant over a wide range of vset pin settings, allowing the part to be adjusted dynamically without affecting conversion gain. the current adjustment can be made by connecting a resistor from the vset pin to the positive supply to in crease the bias current or from the vset pin to ground to decrease the bias current. optionally , the vset pin can be connected to the deto pin to provid e automatic setting of the mixer core current. mixer core the ADL5801 has a double - bal anced mixer that u se s high per - formance sige npn transistors. this mixer is based on the gilbert cell design of four cross - connec ted transistors. mixer output load the mixer load uses a pair of 125 resistors connected to the positive supply. this provides a 250 differential output resis - tance. the mixer output should be pulled to the positive supply externally using a pair of rf chokes or using an output trans - former with the center tap connected to the positive supply . it is possible to exclude these components when the mixer core current is low, but both p1db input and ip3 input are then reduced. the mixer load output can operate from direct current (dc) up to approximately 6 00 mhz into a 200 load. for upconversion applications, the mixer load can be matched using off - chip matching components. transmit operation up to 2 ghz is possible. see the applications information section for matching circuit details. rf detector a n rf power detector is buffered from the v - to - i converter section. this detector has a power response range from approximately ? 25 dbm up to 0 dbm and provide s a current output. the output current is designed to be connected to the vset pin to boost the mixer core current when large rf signal s are present at the mixer input. a n external capacitor can be used to adjust the response time of this function. if not used, the deto pin can be left open or connected to ground.
ADL5801 rev. 0 | page 12 of 20 bias circuit a band gap reference circuit generates the reference cur rents used by mixers . the bias circuit can be enabled and disabled using the enbl pin. if the e nbl pin is grounded or left open, the part is enabled. pulling the enbl pin high shuts off the bias circuit and disables the part. however, the enbl pin does not alter the current in the lo section and, therefore, does not provide a true power - down feature . in addition, if the vset pin is connected to the positive supply through a resistor to increase the mixer core current, this continues to provide bias current to the mixer core unless the resistor supply is also removed.
ADL5801 rev. 0 | page 13 of 20 applications informa tion basi c connections the ADL5801 is designed to translate between radio frequencies (rf) and intermediate frequencies (if). for both upconversion and downconversion applications, rfip (pin 16) and rfin (pin 15) must be configured as the input interfaces. ifop ( pin 20) and ifon (pin 21) must be configured as the output interfaces. individual bypass capacitors are needed in close proximity to each supply pin (pin 7, pin 13, pin 18, and pin 24), the vset control pin (pin 10), and the deto detector output pin (pin 1 1). when the on - chip detector is chosen to form a closed loo p , automatically controlling the vset pin, r7 can be populated with a 0 ? resistor . alternatively , simply use a jumper between the vset and deto test points for evaluation. figure 28 illustrates the basic connections for adl580 1 operation. rf and lo ports the rf and lo input ports are designed fo r a differential input impedance of approximately 50 ?. figure 29 and figure 30 illustrate the rf and lo interfaces, respectively. it is recommended that each of the rf and lo differential ports be driven through a balun for optimum performance. it is also necessary to ac couple both rf and lo ports. using proper value capacitors may help improve the input return loss over desired frequencies. table 4 lists the recommended compone nts for various rf and lo frequency bands. the characterization data is available in the typical performance characteristics section. gnd vplo enbl vset vpdt rfip nc gnd gnd vplo loip t2 t4 t7 t3 t6 t9 c4 c5 c50 c6 c1 c12 c18 c8 c10 c9 c2 c3 t1 t5 t8 c17 vpos vset r10 r9 r7 vpos vpos vpos ifop loip loin c7 vpos deto loin gnd gnd ADL5801 gnd gnd ifon deto gnd vprf gnd gnd ifop rfin 24 1 2 3 4 5 7 8 9 10 11 12 6 18 17 16 15 14 13 23 22 21 20 19 08079-128 ifon enbl r12 r8 rfip rfin r4 r16 r14 c20 r50 c19 c13 l3 l1 l4 l5 l2 r3 r 1 3 r 1 1 r2 figure 28 . basic connections schematic
ADL5801 rev. 0 | page 14 of 20 rfip t3 c 8 c 9 rfip adl 5 801 gnd gnd rfin 17 16 15 14 08079-129 figure 29 . rf interface gnd loip t2 c4 c5 loip loin gnd gnd ADL5801 gnd 1 2 3 4 5 6 08079-130 figure 30 . lo interface table 4 . suggested components for the rf and lo interfaces rf and lo frequency t1, t3, t5 c8, c 9 c 4 , c 5 900 mhz mini - circuits? tc1 -1 - 13m+ 5.6 pf 100 pf 1 900 mhz mini - circuits tc1 -1 - 13m+ 5.6 pf 100 pf 2500 mhz mini - circuits tc1 -1 -43+ 2 pf 8 pf if port the if port features an open - collector , differential output interface. it is necessary to bias the open collector outputs using one of the schemes presented in figure 31 and figure 32. figure 31 shows the use of center - tapped impedance transformers . the turns ratio of the transformer should be selected to provide the desired impeda nce trans formation. in the case of a 50 load impedance, a 4:1 impedance ratio transformer should be used to transform the 50 load into a 200 differential load at the if output pins. figure 32 shows a differential if interface where pull - up choke inductors are used to bias the open - collector outputs. the shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the if frequency of operation not to load down the output current bef ore it reaches the intended load. additionally, the dc current handling capability of the selected choke inductors must be at least 45 ma . the self - resonant frequency of the selected choke inductors must be higher than the intended if frequency. a variety of suitable choke inductors is commercially available from manufacturers such as coilcraft and murata. an impedance transforming network may be required to transform the final load impedance to 200 at the if outputs. nc gnd c50 c13 l3 r3 r2 t1 t5 t8 vpos ifop gnd ifon ifop 23 22 21 20 19 a d l 5 8 0 1 08079-131 figure 31 . biasing the if port open - collector outputs using a center - tapped impedance transformer nc gnd c20 c19 c13 l3 l1 l2 r3 r2 t1 t5 t8 vpos vpos gnd ifon ifop 23 22 21 20 19 ADL5801 z l impedance transforming network 08079-132 figure 32 . biasing the if port open - collector outputs using pull - up choke inductors
ADL5801 rev. 0 | page 15 of 20 e valuation board an evaluation board is a vailable for the ADL5801. the standard evaluation board is fabricated using rogers? ro3003 mat erial. each rf, lo, and if port is configured for single - ended signaling via a balun transformer. the schematic for the evaluation board is shown in figure 33. table 5 describes the various configuration options for the evaluation board. layout for the board is shown in figure 34 and figure 35. gnd vplo enbl vset vpdt rfip nc gnd gnd vplo loip r14 r16 t2 t4 t7 t3 t6 t9 c4 c5 c20 r50 c50 c6 c1 c12 c18 c8 c10 c19 c13 l3 l1 l2 c9 l4 r3 c2 c3 r13 r11 r2 t1 t5 t8 l5 c17 c11 r7 r9 r10 r12 r8 rfip vpos vpos vpos vset vpos ifop loin loip ifon rfin c7 vpos enbl deto loin gnd gnd ADL5801 gnd gnd ifon deto gnd vprf gnd gnd ifop rfin 24 1 2 3 4 5 7 8 9 10 11 12 6 18 17 16 15 14 13 23 22 21 20 19 08079-133 figure 33 . evaluation board schematic
ADL5801 rev. 0 | page 16 of 20 table 5 . eval uation board configuration components function default conditions c2, c3, c6, c7, c10, c11 power s upply d ecoupling. nominal supply decoupling consists of a 0.1 f cap ac itor to ground in parallel with 100 p f capacitors to ground , positioned as close to the device as possible. series resistors are provided for enhanced supply decoupling using optional ferrite chip inductors. c2, c6, c10, c11 = 0.1 f (size 0402) c3, c7 = 100 pf (size 0402 ) c8, c9, l4, l5, r4, r8, r12, t3, t6, t9, rf in, rfip rf i nput i nterface s . input ch annels are ac - coupled through c 8 and c9. r8 and r1 2 provide options when additional matching is needed. t3 is a 1:1 ba lun used to interface to the 50 differential inputs. t6 and t9 provide options when high frequency baluns are used and require smaller balun footprints. c8, c9 = 5.6 pf (size 0402) l4, l5, r12 = 0 (size 0402) r4, r8 = open (size 0402) t3 = tc1 -1 - 13m+ (mini - circuits) c13, c19, c20, c 50, l1, l2, l3, r2, r3, r11, r13, r50, t1, t5, t8, if on, ifop if output i nterface s . the 200 open collector if output interfaces are biased through the center tap of a 4:1 impedance transformer at t1. c50 provides local bypassing with r50 available for ad ditional supply b ypassing. l1 and l2 provide options when pull - up choke inductors are used to bias the open - c ollector outputs. c13, l3, r2 , and r3 are provided for if filtering and matching options. t5 and t8 provide options when high frequency baluns are used and require smaller balun footprints. c13 = open (size 0402) c19, c20 = 100 pf (size 0402) c50 = 0.1 f (size 0402) l1, l2 = open (size 0805) l3 = open (size 0402) r2, r3, r13, r50 = 0 (size 0402) r11 = open (size 0402) t1 = tc4 - 1w+ (mini - circuits ) c4, c5, r14, r16, t2, t4, t7, lo in, loip lo i nterface. c4 and c5 provide ac coupling for the local oscilla tor input. t2 is a 1:1 balun that allow s single - ended interfacing to the differential 50 local oscillat or input. t4 and t7 provide options when hi gh frequency baluns are used and require smaller balun footprints. c4, c5 = 100 pf (size 0402) r14 = 0 (size 0402) r16 = open (size 0402) t2 = tc1 -1 - 13m+ (mini - circuits) c1, c12, r7, deto deto i nterface. c1 an d c12 provide decoupling for the deto pin . r 7 provide s access to the vset pin when automatic input ip3 control is needed. c1 = 0.1 f (size 0603 ) c12 = 100 p f (size 0402 ) r7 = open (size 0402) c17, c18, r9, r10, vset vset b ias c ontrol . c17 and c18 provide decoupling for the vset pin . r9 and r10 for m an optional resistor divider network between v pos and gnd, allowing for a fixed bias setting. supply 3.8 v at the vset pin when the deto pin is not connected for automatic input ip3 control. c17 = 100 p f (size 0402 ) c18 = 0.1 f (size 0603 ) r9, r10 = ope n (size 0402) 08079-134 figure 34 . evaluation board top layer 08079-135 figure 35 . evaluation board bottom layer
ADL5801 rev. 0 | page 17 of 20 outline dimensions compliant to jedec standards mo-220-vggd-8 1 24 6 7 13 19 18 12 2.65 2.50 sq 2.35 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min exposed pa d (bo tt om view) 082908-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 36 . 24 - lead lead frame chip scale package [lf csp_vq] 4 mm 4 mm body, very thin quad (cp - 24 - 3) dimensions shown in millimeters ordering g uide model 1 temperature range package description package option ordering quantity ADL5801 a cpz -r7 ? 40c to +85c 24- lead lead frame chip scale package [lfcsp_vq ] cp -24-3 1,500 per reel ADL5801 - evalz evaluation board 1 1 z = rohs complaint part.
ADL5801 rev. 0 | page 18 of 20 notes
ADL5801 rev. 0 | page 19 of 20 notes
ADL5801 rev. 0 | page 20 of 20 notes ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08079 - 0 - 2/10(0)

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